1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a wafer that uses a silicon nanowire buffer layer to insulate a compound semiconductor from thermally-induced lattice mismatches with an underlying silicon (Si) substrate.
2. Description of the Related Art
Gallium nitride (GaN) is a Group III/Group V compound semiconductor material with wide bandgap (3.4 eV), which has optoelectronic, as well as other applications. Like other Group III nitrides, GaN has a low sensitivity to ionizing radiation, and so, is useful in solar cells. GaN is also useful in the fabrication of blue light-emitting diodes (LEDs) and lasers. Unlike previous indirect bandgap devices (e.g., silicon carbide), GaN LEDs are bright enough for daylight applications. GaN devices also have application in high power and high frequency devices, such as power amplifiers.
GaN LEDs are conventionally fabricated using a metalorganic chemical vapor deposition (MOCVD) for deposition on a sapphire substrate. Silicon carbide (SiC) substrates are also used due to their relatively small lattice constant mismatch. However, these substrates are expensive to make, and their small size also drives fabrication costs. For example, the state-of-the-art sapphire wafer size is only about 4 inches. To minimize costs, it would be desirable to integrate GaN device fabrication into more conventional Si-based IC processes, which has the added cost benefit of using large-sized (Si) wafers.
Silicon attracted attention as a substrate material for GaN growth when the first molecular beam epitaxy (MBE) grown GaN LED on Si was demonstrated in 1998. This work also demonstrated that p-type doping was achievable in GaN. Nevertheless, until recently, the properties of GaN-on-Si devices have been poor. For example, the full wave at half maximum (FWHM) of an X-ray rocking curve for GaN-on-Si may be 1000 arc s, whereas the measurement for a comparable GaN-on-SiC device may be 250-300 arc s. The photoluminescence spectra of the films grown on Si also show peak broadening.
There are two fundamental problems associated with GaN-on-Si device technology. First, there is a lattice mismatch of almost 16% between Si and GaN. This problem can be addressed by using a buffer layer of AlN, InGaN, AlGaN, or the like, prior to the growth of GaN. The buffer layer provides a transition region between the GaN and Si.
However, an additional and more serious problem exists, as there is also a thermal mismatch between Si and GaN. The thermal expansion coefficient mismatch between GaN and Si is about 54%. Although the lattice buffer layer may absorb part of the thermal mismatch, the necessity of using temperatures higher than 1000° C. during epi growth and other device fabrication may cause wafer deformation. The wafer deformation can be reduced with a very slow rate of heating and cooling during wafer processing but this adds additional cost to the process, and doesn't completely solve the thermal stress and wafer deformation issues. Patterning a substrate, by masking or etching the substrate or buffer layer, is an effective way to reduce lattice mismatch and thermally-induced stress or cracks. In this technique, a buffer layer, Si3N4 or SiO2 for example, is deposited over a Si substrate in a patterned manner, or deep trenches are made on the masked materials. However, this solution adds additional fabrication steps to the process. Other solutions, which incompletely address the problem, involve the use of a doped buffer layer or superlattice structure.
It would be advantageous if the thermal and lattice mismatch problems associated with GaN-on-Si device technology could be practically eliminated without using slow heating and cooling processes, or complicated buffering structures.